IBM 440
Drivers
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Functional requirements

Operating system No kernel application for testing
Device Control Registers
ETC: 2 days
CLI will provides access to the device control registers - commands mfdcr and mtdcr.
Serial Port (UART)
ETC: 2 weeks
...contains two universal asynchronous receiver/transmitters (UARTs) which provide two fullduplex serial interfaces to support communications with serial peripheral devices.
Driver will require from application to fill initialization structure with fields
  • Interrupt/polling mode
  • Initial rate
  • Device number (0 or 1)
  • Signal/Semaphore interface (optional)
  • Mutex (optional)
  • Tick notification (optional)
Serial port driver will simply memcpy() block sent by the application and copy received data to the the blocks provided by the applcation in the call to receive(). Driver does not contain any tasks. This is up to application to create a task calling receive(). Driver makes no assumptions about availability of signal/semaphore API in the underlying OS. Optionally application can provide callback functions implementing init(), wait(), notify() and close() interface. For example, in the interrupt mode driver can call to notify() and in the receive() to wait(). Driver provides trivial implementation of the callbacks - empty functions. Baudrate can be changed online. Driver API is not reentrant if application does not provide mutex as part of the initialization structure.
The following debug CLI commands are available
  • Message/byte rate last Xs (requires tick notification)
  • Total number packet/bytes
  • Total number of errors
  • Reset statistics
  • Force transmit - pattern, burst size, interburst delay
  • Loop test - start loop test, test timeout
  • Echo on/off
  • Set rate
IIC (I2C)
ETC: 1 week
IBM 440 provides two IIC -
two wire, bi-directional, open-drain, low-speed serial interface ... support multiple bus masters ... high- and low-speed devices on the same bus
Driver requirements TBD
GPIO
ETC: 1 week
see also 25.3 GPIO Interface Signals p.824
CLI will provide following commands
  • Set three-state, output (open drain), input
  • Read the signal (if input) How i can test JMPs ? (TBD)
  • Write the signal (if output)
  • Continously toggle the signal from specified interrupt (only timers ?) at specified frequency
  • Turn the group on/off - set specified by mask signals to output and write 1/0 (LED test)
EMAC to PHY Bridge
ETC: TBD
Fixed initialization ? how i can check all signals ? TBD
Direct Memory Access (DMA)
ETC: 2 weeks
The controller provides four DMA channels, each of which has an independent set of configuration registers.
Driver will provide access to all 4 channels. Only very basic memcpy() like mode will be supported. Application will call the driver to setup data transfer and check status of previously started data transfer.
The following debug CLI commands are available
  • Start test - pattern, burst size, interburst delay, from address, to address
  • Stop test
  • Check data
General Purpose Timer (GPT)
ETC: TBD
Start, stop, read, reset (?) TBD
Universal Interrupt Controllers
ETC: TBD
Enable/disable/count events/SW simulation (?) TBD
On-Chip Peripheral Bus
ETC: TBD
Latency, priority, ... Fixed initialization (?) TBD
PLB Performance Monitor
ETC: TBD
Selection Registers to simultaneously track events from up to four selectable PLB masters, up to four PLB slaves and up to four external generic events or pipeline-stage events...All PPM registers are accessed using the mtdcr and mfdcr instructions.
Can not be implemented in ANSI C ?
Ethernet Media Access Controllers
ETC: 1 month
Driver will require from application to fill initialization structure with fields
  • Interrupt/polling mode
  • Device number
  • Signal/Semaphore interface (optional)
  • Mutex (optional)
  • Tick notification (optional)
  • Functions getBlockRx(), freeBlockTx()
Initialization flags
  • Speed
  • Full/half duplex
  • Automatic source address insertion or replacement for transmitted packets
  • Automatic stripping of frame padding bytes and frame check sequence
  • FCS control for transmit/receive packets
  • Selection between MII/RII interfaces
  • Look back
To avoid memcpy() of the packets driver will expect from the application to allocate and release packets. Driver expects that application can release the block by address. Application typically will store pointer to the releasing function at the beginning of the packet before actual data started or in separate arrray. In the later case index in the array can be calculated from the address assuming that all blocks are of the same size. Packets marked this way can be freed and allocated using different functions while driver is completely unaware of this.
Driver provides only one send function - txPacket(). There is no high priority/low priority queues. No support provides for dual tx channel (? see also Migrating to PPC440GX from PPC440GP: Software Considerations::New ethernet functions)
To make driver API reentrant application should provide Mutex structure conatining init(), close(), get(), send() functions.
Application can choose between interrupt, polling or mixed mode. In all cases application has to spawn task calling rxPacket() and provide function wait() implemented by the application. In the polling mode wait() will just pause the rx task for the predefined by the application timeout or in case of no kernel will be an empty function. In the interrupt and mixed mode application will provide signal interface and wait() will call waitSignal(). Interrupt routine implemented by the driver will call provided by the application sendSignal() function.
Driver does not make any additional memory allocation besides memory provided by the application as part of the initialization structure.
The following debug CLI commands are available
  • Message/byte rate last Xs (requires tick notification)
  • Total number packet/bytes
  • Number of errors gripued by type and total
  • Reset statistics all and grouped
  • Force transmit - pattern, burst size, interburst delay
  • Loop test - start loop test, test timeout
  • Echo on/off (echo all received data)
  • Access to all EMAC counters
  • Pause transmit/receive
  • Stop/start receive/transmit
  • Stop/start operations (full reinitialization and restart)
  • Unicast, multicast, broadcast, and promiscuous address filtering
  • VLAN tag insertion or replacement for transmit packets
  • Error/status vector generation for each processed packet.
FLASH
DRAM
NVRAM
PCI









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